1. Field of the Invention
The present invention relates to a method for storing data in multi-level flash memory cells and a sensing method for reading the stored data.
2. Description of the Related Art
FIG. 1 shows a typical configuration for an integrated circuit including a flash memory array 100 and circuitry enabling programming, erasing, and reading for memory cells in the array 100. The flash memory array 100 is composed of individual cells, such as 102. Each cell has a drain connected to a bitline, such as 104, each bitline being connected to a bitline pull up circuit 106 and column decoder 108. Sources of the array cells are connected to Vss, while their gates are each connected by a wordline to a row decoder 110.
The row decoder 110 receives voltage signals from a power supply 112 and distributes the particular voltage signals to the wordlines as controlled by a row address received from a processor or state machine 114. Likewise, the bitline pull up circuit 106 receives voltage signals from the power supply 112 and distributes the particular voltage signals to the bitlines as controlled by a signal from the processor 114. Voltages provided by the power supply 112 are provided as controlled by signals received from processor 114.
The column decoder 108 provides signals from particular bitlines to sense amplifiers or comparators 116 as controlled by a column address signal received from processor 114. The sense amplifiers 116 further receive voltage reference signals from reference 118. The outputs from sense amplifiers 116 are then provided through data latches or buffers 120 to processor 114.
To program a cell in the flash memory array 100, high gate-to-drain voltage pulses are provided to the cell from power supply 112 while a source of the cell is grounded. For instance, during programming typical gate voltage pulses of 10V are each applied to a cell, while a drain voltage of the cell is set to 5.5V and its source is grounded. This programming procedure results in an increase of a threshold voltage for the cell, the threshold being the gate-to-source voltage required for the cell to conduct.
To erase a cell in the flash memory array 100, relatively high negative gate-to-source voltage pulses are applied. For instance, during erase gate voltage pulses of -10V are applied to a cell, while a drain of the cell is set to 5.5V and its source is floated. The large negative gate-to-source voltage pulses reduce the threshold of the cell.
To read the state of a cell, a typical control gate voltage of 5V is applied to the cell. The current output from the cell being read is received at an input of a number of the sense amplifiers 116 connected to the same bitline as the cell being read. A second input to each sense amplifier is provided from the reference 118. The reference 118 provides a different reference current to each sense amplifier connected to a bit line, with a current level set equal to current expected from a cell being read when programmed to a desired threshold voltage state. Binary outputs of the sense amplifiers 116 indicate if the cell being read is in a state which is greater than or less than the state of the reference signal received. Outputs of the sense amplifiers are provided through data latch/buffers 120 to the processor 114, enabling the processor 114 to determine from the sense amplifier outputs the threshold state of the cell being read.
Multi-level storage refers to the ability of a single memory cell to represent more than a single binary bit of data. A conventional memory cell depicts two states or levels, usually referred to as logic "0" and logic "1". A multi-level cell could represent as many as 256 states, or a byte of information.
Multi-level cell storage is obtainable in flash design because a flash memory cell can be programmed to provide multiple threshold voltage (vt) levels. The different vt levels can be sustained over time in a flash memory cell, even after repeated accesses to read data from the cell. For example, 16 vt levels stored in a flash memory cell can represent data in four conventional memory cells. Thus, an array of multi-level flash memory cells which can store up to 16 vt levels can provide 4 times the storage capacity of conventional memory cells which only store a binary bit per cell.
Table 1 below shows typical vt levels of a flash memory cell capable of storing up to 16 vt levels, along with a hexadecimal representation of the data stored. The hexadecimal number can be represented by 4 binary bits, or a nibble, as indicated by the data indication D(3:0) in Table 1.
TABLE 1 ______________________________________ Vt(V) D(3:0) Vt(V) D(3:0) ______________________________________ 0 0 1.0 8 0.125 1 1.125 9 0.250 2 1.250 A 0.375 3 1.375 B 0.500 4 1.500 C 0.625 5 1.625 D 0.750 6 1.750 E 0.875 7 1.875 F ______________________________________
Table 2 below shows typical data stored in four addresses 100-103, the four address being shown in a first column of Table 2. With data in each address being represented by two 16 vt level flash memory cells, the data for each address is represented with two hexadecimal numbers, as shown in a second column of Table 2 beneath the indication D(7:0). The D(7:0) indication shows that 8 binary bits would be required to represent the data in each address. A third column beneath the heading D(7:4), and fourth column beneath the heading D(3:0) in Table 2 show an equivalent binary representation of data stored in the addresses 100-103.
TABLE 2 ______________________________________ Address D(7:0) D(7:4) D(3:0) ______________________________________ 100 AA 1010 1010 101 55 0101 0101 102 84 1000 0100 103 OF 0000 1111 ______________________________________
Table 3 below shows another representation of the data of Table 2, with eight 16 vt level flash memory cells, labeled B0-B7, represented for storing the data in a conventional fashion. In a first row of Table 3, the addresses 100-103 are shown, in a second row the multi-level flash memory cells B0-B7 used to store data for each of the addresses 100-103 are represented, and in a third row the hexadecimal representation for the data stored by each of the multi-level flash cells B0-B7 is shown.
TABLE 3 ______________________________________ Address 100 101 102 103 ______________________________________ Physical cell B0 B1 B2 B3 B4 B5 B6 B7 Stored Data(HEX) A A 5 5 8 4 0 F ______________________________________
With conventional programming of multi-level flash memory cells to store data as illustrated in Table 3, to read the data stored at address 102 requires 2 bit lines, one for each flash memory cell B4 and B5, and 30 sense amplifiers. Each bit line is connected to an input of 15 sense amplifiers. Each sense amplifier for a bit line in turn has another input receiving a unique reference corresponding to threshold states between the 16 possible vt states for the flash memory cells. By monitoring the output of the sense amplifiers, the data stored by each flash memory cell can be determined.
The possibility to reduce the number of sense amplifiers exists, but is detrimental to the access time required to read data. For example, in the above case with 8 sense amplifiers per bit line, two sensing operation passes would be required to determine the state stored by a flash memory cell. Multiplexing to select proper references to each sense amplifier during each pass would also be needed. If 4 sense amplifiers are utilized, 4 passes would be required to identify the data stored in a multi-level memory cell.